Reminder: Submission must be on time as discussed in class. Where the solution requires a process, show that process, not simply the solution. Your grade in all the homework assignments and exams depends on the legibility of submission: typing or screen shots preferred, ensuring that page arrangement is all the same direction orientation.
Assigned: 10/15/16 Due: 10/28/16 1
. (2.5 points) Register Operations.
Provided a 16-bit register is currently loaded with the value 1010 1100 0101 0011 (b15 .. b0), (i) what logical operation (e.g., AND, OR, NOT, NAND, NOR, XOR) must be performed with (ii) what 16-bit operand, to meet the following requirements:
a) Clear all odd bit positions to 0.
b) Set the 4 least significant bits to 1.
c) Complement the leftmost 8 bits. a minimum multiple-level gate implementation with minimum gate-input cost using AND and OR gates and inverters.
2. (2.5 points) Register Cell Design. Design the input logic (e.g., AND, OR, NOT gates and wiring) for the 8-bit Register R0 using inputs from 8-bit sensors S0 and S1 along with associated Register R1, given the following register transfer functions:
S1 S0 : R0 ¬ R0 Ù R1
S1 S0 : R0 ¬ R0 Å R1
S1 S0 : R0 ¬ R0 Ú R1
S1 S0 : R0 ¬ R0 Å R1
3. (2.5 points) Washing Machine Controls Design.
Your team will be developing a state machine diagram for a washing machine synchronous control circuit to the following specifications:
External inputs START, FULL, EMPTY: Logic 1 for a clock cycle; mutually exclusive; reflect pushbutton and water level, respectively.
External outputs HOT, COLD, DRAIN, TURN: Logic 1 to fill or drain water (temperature); and to operate washer motor, respectively.
Datapath control: down-counter with 3 inputs: RESET, DEC, LOAD: counter synchronously decrements once per minute for DEC = 1; can be loaded or reset on any cycle of clock CK. Down-counter output: ZERO: Logic 1 when counter is 0; 0 otherwise.
Operation: Circuit life cycle begins and ends in IDLE state, has 4 distinct cycles (e.g., each may have multiple states, dependent on the conditions, where it is within the washer’s life cycle): WASH, SPIN, RINSE, SPIN.
WASH: Washer begins in IDLE. When START signaled (1), HOT set (to 1), filling washer tub until high level sensor indicates FULL (1). Using LOAD, down-counter loaded from user selector knob with the number of minutes the wash cycle will last. Next, DEC and TURN set (to 1) as washer washes clothes. When ZERO becomes 1, wash cycle complete, DEC and TURN cleared (to 0).
SPIN: DRAIN set (to 1) emptying dirty, soapy water in the washer. Once low level sensor indicates EMPTY (1), the down-counter is loaded with ‘7’ and DEC and TURN are set (to 1) to wring remaining water from the clothes. When ZERO becomes 1, spin cycle complete, DRAIN, DEC and TURN cleared (to 0).
RINSE: COLD set (to 1) filling washer tub until high level sensor indicates FULL (1). Downcounter is loaded with ’10’ and DEC and TURN are set (to 1) to rinse the clothes. When ZERO becomes 1, rinse cycle complete, DEC and TURN cleared (to 0).
SPIN: DRAIN set (to 1) emptying rinse water in the washer. Once low level sensor indicates EMPTY (1), the down-counter is loaded with ‘8’ and DEC and TURN are set (to 1) to wring remaining rinse water from the clothes. When ZERO becomes 1, spin cycle complete, DRAIN, DEC and TURN cleared (to 0) and the circuit state returns to IDLE.
a) Design the washing machine circuit state machine diagram.
b) Following presentation of your design, Marketing informs management that consumers require an additional feature; management decides a re-design will lead to greater sales. Your team is now directed to modify the design (above) to include 2 additional inputs, PAUSE and STOP. When PAUSE becomes 1, the circuit halts (including the counter) and all outputs are cleared (to 0). When START becomes 1, washer operation resumes from the point it was paused. When STOP signaled (1), all outputs are reset (to 0), except for DRAIN set (to 1) until EMPTY; then machine returns to IDLE state.
4. (2.5 points) Game Design. Our text describes the game of PIG on pages 376 – 384. Your team is assigned to design the 2- digit Binary-to-BCD Code Converter in its datapath.
b) Design the same circuit with an incoming carry, C0 = 1. If there’s a carry, this will be used; if not, the circuit designed in (a) will be used. Combine both for use in the most significant digit of the 2-digit display. Optimize the circuit to minimize gate inputs.
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